1. Field of the Invention
The present invention relates to a semiconductor integrated circuit device and a method for fabrication thereof, particularly to a bipolar integrated circuit device and a method for production thereof.
2. Description of the Prior Art
Bipolar integrated circuit transistor devices generally have a structure as indicated in FIG. 1. In the same figure, 1 is the P type semiconductor substrate; 2 is the N type epitaxial layer formed on the substrate 1; 3 is the N.sup.+ type buried layer deposited at the boundary of the substrate 1 and epitaxial layer 2; 4 is the P type isolation region formed reaching the substrate 1 from the surface of the epitaxial layer 2. In addition, 5 is the P type base region formed on the epitaxial layer 2 in the element forming region defined by the isolation region 4; 6 is the N.sup.+ type emitter region formed within the base region 5; 7 is the N.sup.+ type collector contact region formed within the epitaxial layer. Moreover, 8 is the insulating film covering the surface of said epitaxial layer 2; 9 is the emitter electrode; 10 is the base electrode; 11 is the collector electrode.
In such a bipolar transistor, the collector consists of the N.sup.+ type buried layer 3 and the N.sup.+ type collector contact region 7. Therefore, a collector series resistance can be lowered and the high operating speed of the relevant bipolar transistor can be improved by forming the buried layer 3 and the collector contact region 7 in proximity to each other, and, when possible, in such a way as to come into contact.
However, according to such production method of the bipolar transistor, the collector contact region 7 is generally formed simultaneously with the emitter region 6 and resultingly it is formed almost in the same depth as the emitter region 6 and does not reach the buried layer 3. Thus the epitaxial layer 2 of lower impurity concentration exists between the collector contact region 7 and the buried layer 3, so that a lowering of the collector series resistance is not achieved. On the other hand, it is also attempted to form a deeper collector contact region 7 by separately forming the emitter region 6 and the collector contact region 7 but such fabrication method results in an increase in fabrication steps.
In order to overcome the difficulty in forming the collector in the conventional bipolar transistor and the fabrication method thereof, a method such as disclosed in the patent application Ser. No. 50-364 (application date: Dec. 23, 1974) has been proposed.
Namely, as indicated in FIG. 2, an insulating film 22 consisting of silicon dioxide is formed in the thickness of about 1 .mu.m on the surface of a P type silicon semiconductor substrate 21.
Then, as illustrated in FIG. 3, the insulating film 22 is selectively removed by etching, thus forming a window 23 with a part of the semiconductor substrate 21 being exposed. At this time, the edge 23A of the window 23 of the insulating film 22 is tapered with an inclination of about 45 degree by properly selecting the etching conditions.
Next, phosphorus ions (P.sup.+) are implanted into the semiconductor substrate 21 using the insulating film 22 as the mask, thereby forming, as illustrated in FIG. 4, the N.sup.+ type buried layer 24 which is flat just under the window 23 and changes continuously in the depth corresponding to an inclination at the area just under the inclining portion of the insulating film 22 and partly extends up to the boundary of the semiconductor substrate 21 and the insulating film 22.
Then, the insulating film 22 is removed and as illustrated in FIG. 5 the insulating film 25 is newly formed on the surface of the semiconductor substrate 21.
Thereafter, a window is provided on the insulating film 25, and phosphorus ions (P.sup.+) are implanted into a P type region 26 surrounded by the N.sup.+ type layer 24 and the exposed area of the N.sup.+ type buried layer 24, thereby as illustrated in FIG. 6, an N.sup.+ type emitter region 27 and an N.sup.+ type collector contact region 28 are formed. In this case, the P type region 26 forms the base region. In the same figure, 29, 30 and 31 are respectively an emitter electrode, a base electrode and a collector electrode.
According to this proposed method, the N.sup.+ type buried layer 24 forms the collector region, and a part of the N.sup.+ type layer 24 can be formed up to the surface of semiconductor substrate using only a single ion implantation process. Therefore, this method is sufficient for forming the collector contact region 28 to the same depth as the emitter region 27, and thereby the production process is simplified over that associated with the structure illustrated in FIG. 1.
However, in such a proposed method, it is difficult to form the tapered portion to the desired inclination at the edge 23A of the window 23 on the insulating film 22 in the process illustrated in the FIG. 3. Namely, after providing the window 23 on the insulating film 22, the tapered portion is formed at the edge 23 of the window 23 by changing the etching solution or changing the mask for etching, thus the process is troublesome and it is difficult to form the window 23 having to the desired inclination angle and size.